• DocumentCode
    390351
  • Title

    Performance evaluation of a parallel-poll virtual output queued switch with two priority levels

  • Author

    Gong, Yiping ; Liu, El

  • Author_Institution
    Dept. of Comput. Sci. & Technol., Tsinghua Univ., Beijing, China
  • Volume
    1
  • fYear
    2002
  • fDate
    29 June-1 July 2002
  • Firstpage
    669
  • Abstract
    Development of high performance switches is of paramount importance in high bandwidth connection networks. Input buffered switches with virtual output queues (VOQ) are most impressive because the access rate of crossbar and buffer memory is not higher than the line rate of the connected link. To support various types of traffic with different quality of service (QoS), the packet scheduling algorithms, which solve the contentions in the transfer of data units from an input link to the appropriate output link, must provide different guarantee for different types of traffic. In this paper, based on the parallel-poll VOQ (PP-VOQ) architecture, we propose a simple novel cell scheduling algorithm with two priority levels. We show by simulation that, in the case of cell-based switches, this priority mechanism provide performance advantages over prioritized iSLIP and such an input-queued architecture can provide guaranteed rate, bounded delay, and jitter-restriction for both two priority levels of traffic.
  • Keywords
    buffer storage; delays; jitter; packet switching; quality of service; queueing theory; telecommunication traffic; QoS; access rate; bandwidth connection networks; bounded delay; buffer memory; cell scheduling algorithm; cell-based switches; crossbar memory; data units transfer contentions; guaranteed rate; high performance switches; input buffered switches; input-queued architecture; jitter-restriction; packet scheduling algorithms; parallel-poll VOQ; parallel-poll virtual output queued switch; performance evaluation; prioritized iSLIP; quality of service; simulation experiments; traffic priority levels; virtual output queues; Bandwidth; Computer science; Delay; Packet switching; Quality of service; Scheduling algorithm; Switches; Telecommunication traffic; Throughput; Traffic control;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Communications, Circuits and Systems and West Sino Expositions, IEEE 2002 International Conference on
  • Print_ISBN
    0-7803-7547-5
  • Type

    conf

  • DOI
    10.1109/ICCCAS.2002.1180706
  • Filename
    1180706