Introducing pipelining technique in an object-oriented processor

Author

Lun, Mok Pak ; Fong, Anthony S.

Author_Institution

Dept. of Electron. Eng., City Univ. of Hong Kong, Kowloon, China

Volume

1

fYear

2002

fDate

28-31 Oct. 2002

Firstpage

301

Abstract

A high level instruction set computer (HISC) supports object-oriented programming (OOP) in the hardware level. HISC provides the objects´ information to hardware through the use of tables and a data structure called operand descriptor. An implementation of the HISC architecture, currently named jHISC, is under research. It is a 64-bit processor that developed mainly targets for JAVA. In this paper, we discuss how the jHISC processor can use the pipelining technique to enhance the performance. We start from defining the stages in HISC, then the architectural design. Finally, some issues in the implementation of jHISC on FPGA are discussed.

Keywords

computer architecture; data structures; field programmable gate arrays; object-oriented programming; performance evaluation; pipeline processing; 64 bit; 64-bit processor; FPGA; HISC architecture; OOP; architectural design; data structure; high level instruction set computer; jHISC; object-oriented processor; object-oriented programming; operand descriptor; performance; pipelining technique; software development; tables; Computer aided instruction; Computer architecture; Data structures; Decoding; Hardware; Java; Logic; Object oriented programming; Pipeline processing; Security;

fLanguage

English

Publisher

ieee

Conference_Titel

TENCON '02. Proceedings. 2002 IEEE Region 10 Conference on Computers, Communications, Control and Power Engineering

Print_ISBN

0-7803-7490-8

Type

conf

DOI

10.1109/TENCON.2002.1181274

Filename

1181274