Frequency jitter of a digital phase-locked loop and comparison with a modified CRB

Author

Kandeepan, Sithamparanathan ; Reisenfeld, Sam

Author_Institution

Fac. of Eng., Univ. of Technol., Sydney, NSW, Australia

Volume

1

fYear

2002

fDate

25-28 Nov. 2002

Firstpage

96

Abstract

The steady state (SS) noise performance of a digital phase locked loop (DPLL) is of very much interest, while tracking carrier signals. In the literature the SS performance is very well examined in terms of the SS phase jitter, however the SS frequency jitter of a DPLL is unexamined up to now. In this paper we analyse the SS performance of a DPLL in terms of the frequency jitter. We derive a linearised expression for the SS frequency jitter of a DPLL, and verify it by simulations.

Keywords

digital phase locked loops; jitter; parameter estimation; tracking; DPLL; SS phase jitter; carrier signals tracking; digital phase locked loop; digital phase-locked loop; frequency estimator; frequency jitter; linearised expression; lower bound; modified CRB; modified Cramer-Rao bound; parameter estimator; simulations; steady state noise performance; Australia; Cyclic redundancy check; Frequency estimation; Jitter; Mathematical model; Phase detection; Phase locked loops; Satellites; Steady-state; Systems engineering and theory;

fLanguage

English

Publisher

ieee

Conference_Titel

Communication Systems, 2002. ICCS 2002. The 8th International Conference on

Print_ISBN

0-7803-7510-6

Type

conf

DOI

10.1109/ICCS.2002.1182445

Filename

1182445