Submodule construction for timed systems

Addresses the problem of designing a submodule of a given timed system. For representing specifications, we use the model of communicating timed input/output automata. The problem may be formulated mathematically by the equation (C||X)ℜA under the constraint I_n, where C represents the specification of the known part of the system, called the context, A represents the specification of the desired whole system, X represents the specification of the submodule to be constructed, || is a composition operator, ℜ is a conformance relation and I_n is the required set of inputs for X. As conformance relation, we consider the safe realization relation. This relation is implied by all the well-known criteria of trace equivalence, complete trace equivalence, quasi equivalence and reduction. We propose an algorithm for solving the problem with respect to the safe realization and we characterize the set of solutions.