Title :
A Multichannel Serial Link Receiver With Dual-Loop Clock-and-Data Recovery and Channel Equalization
Author :
Kalantari, Nader ; Buckwalter, James F.
Author_Institution :
Mindspeed Technol., Newport Beach, CA, USA
Abstract :
This paper presents a four channel receiver for high-speed signal conditioning. Each channel consists of a continuous time linear equalizer (CTLE) and a dual loop CDR with phase-interpolator. All channels share a single PLL that generates and distributes quadrature clock phases to each CDR for data recovery. Clock amplitude, phase INL and phase DNL are derived for IQ phase error and predict phase-dependent jitter contributions to the recovered clock. The multilane receiver was designed in 130-nm CMOS technology. The die occupies an area of 1930 μm by 1250 μm and consumes 67.9 mW per channel. It achieves a maximum data rate of 7 Gbps per channel for 0 and ±200 ppm clock frequency deviation.
Keywords :
CMOS analogue integrated circuits; clock and data recovery circuits; equalisers; interpolation; jitter; phase locked loops; signal conditioning circuits; CMOS technology; IQ phase error; PLL; bit rate 7 Gbit/s; channel equalization; clock amplitude; clock frequency deviation; continuous time linear equalizer; dual loop CDR; dual-loop clock-and-data recovery; high-speed signal conditioning; multichannel serial link receiver; multilane receiver; phase DNL; phase INL; phase interpolator; phase-dependent jitter contribution prediction; power 67.9 mW; quadrature clock phase distribution; quadrature clock phase generation; size 130 nm; Bit error rate; clock and data recovery; continuous time linear equalizer; jitter generation; phase interpolator; phase locked loop; spread spectrum clocking;
Journal_Title :
Circuits and Systems I: Regular Papers, IEEE Transactions on
DOI :
10.1109/TCSI.2013.2256172
