A mixed abstraction level co-simulation case study using SystemC for system on chip verification

This paper focuses on co-simulation scenarios and their applications as a part of a system-on-chip (SoC) modeling and design methodology developed at Alcatel Microelectronics (now part of STMicroelectronics) within a wireless local area network (LAN) SoC project. This methodology proposes to build a SystemC-based executable model of the system to maintain a bridge between the algorithmic and the implementation worlds. The model is used in later phases by means of co-simulation of SystemC, HDL and firmware. SystemC-HDL co-simulation scenario provides a way of checking inter-operability of a single designed HW module with the SystemC model. The SystemC-instruction set simulator (ISS) co-simulation provides a platform to develop and verify the firmware that will run on the selected processor core even before the HW modules are designed. It is shown that, with sufficient tool support, these design stages reduce the complexity of the SoC design and improve the debugging capabilities.