SystemC-VHDL co-simulation and synthesis in the HW domain

Embedded systems design requires the development of complex HW modules to cope with the most stringent timing constraints of the specifications. This implies the need to update and enrich HW design methodologies to face abstraction and novel requirements. Here we present some results of design practice of HW modules in this context. Co-simulation and synthesis are combined in this approach to achieve higher abstraction levels in the design, to improve validation and re-use of previous designs and human experience. The proposed methodology is embedded in a SystemC based design flow. The SystemC-VHDL co-simulator tool is also based on a SystemC/C++ front-end developed to support the co-simulation between VHDL and SystemC. The prototypal state of the adopted tools increase the novelty and interest of the approach.