Title :
Implementation of a programmable phased logic cell [FPGA]
Author :
Aydin, Mahir ; Traver, Cherrice
Author_Institution :
Union Coll., USA
Abstract :
Traditional field programmable gate arrays (FPGAs) have been controlled by a global clock, which means that all signals have to be routed efficiently to meet the synchronous timing constraints. A phased logic FPGA does not require a global clock; it accomplishes its synchronization by encoding value and timing information of a single bit with two separate wires. In this project, two standard cell designs for a phased logic FPGA were simulated, fabricated in 0.5 μm and 1.5 μm CMOS technologies, and tested successfully.
Keywords :
CMOS logic circuits; circuit simulation; field programmable gate arrays; integrated circuit design; logic design; logic simulation; synchronisation; timing; 0.5 micron; 1.5 micron; CMOS; field programmable gate arrays; phased logic FPGA; programmable phased logic cell; separate single bit wires; single bit value encoding; synchronization; timing information; CMOS logic circuits; CMOS technology; Clocks; Encoding; Field programmable gate arrays; Logic testing; Programmable logic arrays; Synchronization; Timing; Wires;
Conference_Titel :
Circuits and Systems, 2002. MWSCAS-2002. The 2002 45th Midwest Symposium on
Print_ISBN :
0-7803-7523-8
DOI :
10.1109/MWSCAS.2002.1186787
