Title :
A high-throughput pipelined architecture for blind adaptive equalizer with minimum latency
Author :
Mizuno, Masashi ; Ueda, Kenji ; Okello, James ; Ochi, Hiroshi
Author_Institution :
Fac. of Comput. Sci. & Syst. Eng., Kyushu Inst. of Technol., Iizuka, Japan
Abstract :
In this paper, we propose a pipelining architecture for the FIR portion of the multilevel modified constant modulus algorithm (MMCMA). We also provide the correction factor that mathematically converts the proposed pipelined adaptive equalizer into an equivalent non-pipelined conventional MMCMA based equalizer. The proposed pipeline method uses modules with 6 filter coefficients, resulting in an overall latency of a single sampling period along the main transmission line. The basic concepts of the proposed architecture is to implement the FIR filter and the algorithm portion of the equalizer such that the critical path has one complex multiplier and two adders.
Keywords :
FIR filters; adaptive equalisers; adders; blind equalisers; circuit simulation; digital arithmetic; logic design; logic simulation; pipeline processing; FIR filter; MMCMA; adder; blind adaptive equalizer; complex multiplier; correction factor; filter coefficient modules; high-throughput pipelined architecture; main transmission line; minimum latency adaptive equalizer; multilevel modified constant modulus algorithm; sampling period; Adaptive equalizers; Blind equalizers; Computer architecture; Convergence; Delay; Finite impulse response filter; Pipeline processing; Quadrature amplitude modulation; Signal restoration; Throughput;
Conference_Titel :
Circuits and Systems, 2002. MWSCAS-2002. The 2002 45th Midwest Symposium on
Print_ISBN :
0-7803-7523-8
DOI :
10.1109/MWSCAS.2002.1186789