SoC interconnect in deep submicron

The migration to using ultra deep-submicron (UDSM) processes of 0.25 μm or below has enabled the integration of complete electronic systems onto one single chip. These systems-on-chip (SoCs) introduce various challenges in terms of design flows and CAD tools. A design methodology that allows component reuse and intellectual property is necessary for achieving the required functionality, performance and testability while minimizing the cost and time to market. This design methodology relies on the use of a standardized connection interface like a shared bus, which presents increasing difficulties in SoC. This paper describes research directions and various levels of design abstraction to increase the performance of interconnects. These directions include approaches to adopt new analytical models for interconnects and ways to face these challenges early in the design flow. To maximize the benefits of this paper, an extensive set of references is given.