Minimum cost complex resource FPGA partition with performance refining

In this paper, we provide a minimum cost partition algorithm with performance refining for complex resource FPGAs. The ILP solver, LINGO, is employed to find the number of the FPGA chips of each type to minimize the total resource cost. Then we perform delay analysis on the given circuit such that the critical paths can be found during circuit partitioning. Finally, a maximum matching based algorithm cooperated with node ordering is used to partition the given circuit and map it into the corresponding resources of targeted FPGAs. Experiment results on the MCNC LGSynth91 benchmark show that our algorithm not only can implement test circuits with the minimum cost but also can further improve their performance. When we applied node ordering and weight enhancement for nodes on critical paths the performance of partitioned circuits can be further improved compared to that of Y.C. Lin et al (IEEE APCCAS, pp. 556-559, 2000).