Title :
Technology-independent delay optimization of complex CMOS circuitries
Author :
Seidel, Peter-Michael
Author_Institution :
Dept. of Comput. Sci. & Eng., Southern Methodist Univ., Dallas, TX, USA
Abstract :
We extend the model of logical effort for technology-independent delay analysis and optimization of complex CMOS circuitries considering optimized gate sizing and buffer insertion. We are applying the proposed delay optimization procedure to the implementation of a fast dual path FP-adder with irregular structure.
Keywords :
CMOS logic circuits; adders; circuit optimisation; delays; integrated circuit modelling; logic design; CMOS circuit; buffer insertion; dual path FP-adder; gate sizing; logical effort model; technology-independent delay optimization; Adders; CMOS logic circuits; CMOS technology; Computer science; Delay; Hardware; Latches; Logic circuits; Optimization methods; Semiconductor device modeling;
Conference_Titel :
Circuits and Systems, 2002. MWSCAS-2002. The 2002 45th Midwest Symposium on
Print_ISBN :
0-7803-7523-8
DOI :
10.1109/MWSCAS.2002.1186861
