Title :
Spike delay controllable neuron [pattern recognition application]
Author :
Fujii, R.H. ; Sase, G. ; Konishi, Y.T. ; Amin, H.
Author_Institution :
Univ. of Aizu, Fukushima, Japan
Abstract :
The circuit design of an analog/digital spiking neuron with controllable spike delay is proposed. The circuits were simulated using Cadence´s SpectreS simulator and BSIM3 AMI 0.6 μm geometry MOS transistor parameters provided by MOSIS. The estimated static power dissipation was 280 pW for the dendrite and 56 pW for the soma. Dynamic power dissipation was approximately 11.1 pJ/dendrite input switching and 4 pJ/soma output spike switching. A pattern recognition application using this spiking neural network is presented.
Keywords :
MOS integrated circuits; circuit simulation; integrated circuit design; mixed analogue-digital integrated circuits; neural chips; pattern recognition; 0.6 micron; 280 pW; 56 pW; MOS transistor circuit; analog/digital spiking neuron; dendrite input; dynamic power dissipation; pattern recognition; soma output; spike delay controllable neuron; spiking neural network; static power dissipation; Ambient intelligence; Circuit simulation; Circuit synthesis; Delay; Geometry; MOSFETs; Neurons; Pattern recognition; Power dissipation; Solid modeling;
Conference_Titel :
Circuits and Systems, 2002. MWSCAS-2002. The 2002 45th Midwest Symposium on
Print_ISBN :
0-7803-7523-8
DOI :
10.1109/MWSCAS.2002.1186915
