Implementation of 1.5 V low power two-path decimation filters for communications Δ-Σ converters

This paper reports on the fabrication of a low power decimation filter with a two-path architecture. The filter reduces the power consumption by better than 50% over previous work. Instead of decimating data after filtering, the reported technique takes advantage of binary coefficients and performs data division before filtering. Based on the two-path architecture, the adder clock rate as well as the number of additions is reduced. As a result, overall power efficiency is increased by a factor of better than two. Power is further reduced by implementing the design on Silicon-On-Sapphire (SOS) process with the reduction of drain-to-body capacitors. The presented two-path filter has greater attenuation and a narrower transition band than an equivalent implementation of a Sinc filter although with somewhat greater complexity. The selected approach of FIR architecture with its linear phase and excellent delay power product is well suited for communications Δ-Σ ADCs. The 64 times decimation filter was implemented in Peregrine SOS with a 4-bit input and an 18-bit output data width. The filter was functionally tested and operational up to 23 MHz or 0.36 Msps with a power dissipation of 8.3n W/Hz. Powered at 1.5 V and operating at 10 Msps, the filter consumes 1.5 μW at standby and 85 mW at operation.