Advantages of high-pass ΔΣ modulators in interleaved ΔΣ analog to digital converter

ΔΣ modulators are widely used for low to moderate rate analog-to-digital conversions. But they are not adapted to high rate conversion because of the time over-sampling requirement. The use of parallel architecture is one of solutions to increase the frequency range of ΔΣ ADCs. In this paper, we propose using high-pass AY modulators in time-interleaved ΔΣ ADC. The use of high-pass ΔΣ modulators not only retains the performance of the converter but also eliminates the low frequency noises. It allows then to use simple adaptive channel gain equalization schemes to minimize the effects of the channel gain mismatches. Such an architecture can be obtained without adding much hardware complexities. In consequence, the architecture offers the potential of integrating high-precision, high-speed ADC together with digital signal processing functions using VLSI processes optimized for digital circuitry. The paper presents the general architecture and provides a performance analysis closely supported by computer simulations.