DocumentCode
391860
Title
Substrate coupling fault testing in system-on-a-chip digital circuits
Author
Chan, Henry H Y ; Zilic, Zeljko
Author_Institution
Dept. of Electr. & Comput. Eng., McGill Univ., Montreal, Que., Canada
Volume
1
fYear
2002
fDate
4-7 Aug. 2002
Abstract
Modern System-on-a-Chip (SoC) systems are implemented using deep submicron technologies and operate at the GHz range. Logic faults caused by substrate coupling becomes a significant concern. Robust SoC designs must be able to predict and test substrate-coupling hazards in the fabricated circuits. In this paper, we devise an efficient testing strategy that identifies excessive substrate coupling. Faults are located based on drive strength and the coupling response from the substrate model.
Keywords
VLSI; fault diagnosis; integrated circuit testing; logic testing; system-on-chip; coupling response; deep submicron technologies; drive strength; logic faults; substrate coupling fault testing; substrate-coupling hazards; system-on-a-chip digital circuits; testing strategy; Circuit faults; Circuit noise; Circuit testing; Coupling circuits; Crosstalk; Digital circuits; Fault diagnosis; Hazards; System testing; System-on-a-chip;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2002. MWSCAS-2002. The 2002 45th Midwest Symposium on
Print_ISBN
0-7803-7523-8
Type
conf
DOI
10.1109/MWSCAS.2002.1187181
Filename
1187181
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