A wire load model for more accurate power estimation

The wire load of the interconnections of standard cells is an important variable for use in power and timing analysis and, in the last years, especially for concurrent synthesis and placement optimization tools. On the one hand wire load models are characterized by pre-layout wirelength estimations and capacitance per unit length is modeled as "weighted average over all metal layers". On the other hand pre-layout wirelength estimations are quite inaccurate and the layer-specific capacitances are very different. As a consequence significant errors are caused when using wire load models for power estimations. In order to improve the accuracy of power estimation on gate level, we present a methodology for the generation of wire load models for standard cell designs in modern deep-submicron technologies with six metal layers.