DocumentCode
391922
Title
Design issues for low voltage, high speed folding and interpolating A/D converters
Author
Carnu, Ovidiu ; Leuciuc, Adrian
Author_Institution
Dept. of Electr. & Comput. Eng., State Univ. of New York, Stony Brook, NY, USA
Volume
1
fYear
2002
fDate
4-7 Aug. 2002
Abstract
In this paper are discussed design issues for a folding and interpolating A/D converter (ADC) in 0.35 μm CMOS technology. A new averaging technique is used for reducing the DNL and INL errors. The goal is a speed of 100 MS/s and a resolution of 10 bits with a supply voltage of 2.5 V or less.
Keywords
CMOS integrated circuits; analogue-digital conversion; integrated circuit design; interpolation; 0.35 micron; 2.5 V; CMOS; DNL errors; INL errors; averaging technique; design issues; folding A/D converter; interpolating A/D converters; resolution; supply voltage; Bandwidth; CMOS technology; Circuits; Energy consumption; Frequency; Interpolation; Low voltage; Preamplifiers; Resistors; Signal generators;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2002. MWSCAS-2002. The 2002 45th Midwest Symposium on
Print_ISBN
0-7803-7523-8
Type
conf
DOI
10.1109/MWSCAS.2002.1187286
Filename
1187286
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