Variable-rate pipelined multiplier design for reconfigurable DSP applications

Author

Hong, Sangjin ; Chin, Shu-Shin ; Connaway, Correy

Author_Institution

Dept. of Electr. & Comput. Eng., State Univ. of New York, Stony Brook, NY, USA

Volume

1

fYear

2002

fDate

4-7 Aug. 2002

Abstract

This paper presents a VLSI design and implementation of a variable-rate multiply-and-accumulate (MAC) block for DSP applications. The pipeline depth of the multiplier is dynamically controlled given the throughput requirement of the application. The depth of pipeline varies at the hardware level which controls the rate of execution to save power consumption. The MAC is targeted for a coarse grain FPGA design to support a wide range of digital signal processing applications. The power consumption is lowered by reducing the unnecessary register switching. The technique is applied to carry-save and Booth recoded multipliers. The MAC circuit is designed in 0.35-μm CMOS processing technology and evaluated for current DSP applications.

Keywords

CMOS digital integrated circuits; VLSI; digital signal processing chips; field programmable gate arrays; multiplying circuits; pipeline processing; 0.35 micron; Booth recoded multipliers; CMOS; VLSI; carry-save multipliers; coarse grain FPGA design; multiply-and-accumulate block; pipeline depth; reconfigurable DSP applications; throughput requirement; unnecessary register switching; variable-rate pipelined multiplier design; CMOS technology; Digital signal processing; Energy consumption; Field programmable gate arrays; Hardware; Pipelines; Registers; Signal design; Throughput; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2002. MWSCAS-2002. The 2002 45th Midwest Symposium on

Print_ISBN

0-7803-7523-8

Type

conf

DOI

10.1109/MWSCAS.2002.1187289

Filename

1187289