DocumentCode :
392233
Title :
High speed memory subsystem for the SIMD/MISD class of advanced embedded computing
Author :
Joshi, A.A.
Author_Institution :
Fac. of Eng., Multimedia Univ., Cyberjaya, Malaysia
fYear :
2003
fDate :
14-15 Jan. 2003
Firstpage :
207
Lastpage :
211
Abstract :
The enhanced high speed RAM is designed for the experimental SIMD/MISD class of computer. The computer is configurable in any of the two said classes. In the total experimental SIMD/MISD class computer, IBM PC will act as a front end system. The RAM becomes a part of the back end system. This paper outlines the design strategy and implementation techniques required for implementing the RAM subsystem.
Keywords :
embedded systems; parallel machines; random-access storage; IBM PC; RAM subsystem; SIMD/MISD; advanced embedded computing; back end system; computer architecture; enhanced high speed RAM; front end system; high speed memory subsystem; mirror RAM design; multiple instruction single data; single instruction multiple data; Application software; Central Processing Unit; Computer aided instruction; Computer architecture; Embedded computing; Mirrors; Random access memory; Read-write memory; Satellites; Testing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Telecommunication Technology, 2003. NCTT 2003 Proceedings. 4th National Conference on
Print_ISBN :
0-7803-7773-7
Type :
conf
DOI :
10.1109/NCTT.2003.1188337
Filename :
1188337
Link To Document :
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