Filling the via hole of IC by VPES (vacuum printing encapsulation systems) for stacked chip (3D packaging)

The most important process for developing 3D packaging, especially wafer stacking, is studied in this paper. That is, the process of filling the via hole. Via holes need to be filled with conductive paste for connection or non-conductive paste for reliability. VPES is useful for the process of filling the paste in small via holes. And this process is also suitable for filling via holes of functional substrates and glass. Many kinds of paste (both conductive paste and nonconductive paste) were studied. It was important that the printing conditions (printing times, vacuum condition etc.) were different for each paste. Printing conditions for each paste were confirmed and the mechanisms for filling the via hole by VPES were identified. The printing conditions depend on the structure of the via hole (design, aspect ratio, diameter and depth etc.), and also the properties of the filling paste (viscosity and thixotropic index etc.).