Title :
The Impact of BTI Variations on Timing in Digital Logic Circuits
Author :
Jianxin Fang ; Sapatnekar, Sachin S.
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Minnesota, Minneapolis, MN, USA
Abstract :
A new framework for analyzing the impact of bias temperature instability (BTI) variations on timing in large-scale digital logic circuits is proposed in this paper. This approach incorporates both the reaction-diffusion model and the charge-trapping model for BTI and embeds these into a temporal statistical static timing analysis framework capturing process variations and path correlations. Experimental results on 32-, 22-, and 16-nm technology models, which were verified through Monte Carlo simulation, confirm that the proposed approach is fast, accurate, and scalable and indicate that BTI variations make a significant contribution to circuit-level timing variations.
Keywords :
logic circuits; stability; statistical analysis; timing circuits; BTI variation; Monte Carlo simulation; charge- trapping model; circuit-level timing variations; digital logic circuits; path correlations; reaction-diffusion model; size 16 nm; size 22 nm; size 32 nm; temporal statistical static timing analysis framework; Analytical models; Charge carrier processes; Correlation; Degradation; Integrated circuit modeling; Timing; Transistors; Bias temperature instability (BTI); circuit reliability; process variation (PV); timing analysis;
Journal_Title :
Device and Materials Reliability, IEEE Transactions on
DOI :
10.1109/TDMR.2013.2237910
