Title :
A proposal for routing-based timing-driven scan chain ordering
Author :
Gupta, Puneet ; Kahng, Andrew B. ; Mantik, Stefanus
Author_Institution :
Dept. of Electr. & Comput. Eng., California Univ., San Diego, La Jolla, CA, USA
Abstract :
Scan chain insertion can have large impact on routability, wirelength and timing. We propose a routing-driven and timing-aware methodology for scan insertion with minimum wirelength. We take into account timing slacks at all sinks that are affected by scan insertion, to achieve a scan chain ordering that meets timing and has smallest wirelength. For the case where sink timing is not met, we also propose a buffer insertion methodology with minimum wirelength objective. The key contribution of this paper is a method to compute a timing-driven incremental connection suited to scan insertion; this has possible applications in general incremental routing.
Keywords :
VLSI; design for testability; integrated circuit design; network routing; shift registers; travelling salesman problems; VLSI; buffer insertion methodology; design for testability; routability; routing; scan chain insertion; scan chain ordering; shift registers; sink timing; timing driven incremental connection; timing slacks; travelling salesman problem; wirelength objective; Circuit testing; Costs; Design for testability; Flip-flops; Pins; Proposals; Registers; Routing; Timing; Traveling salesman problems;
Conference_Titel :
Quality Electronic Design, 2003. Proceedings. Fourth International Symposium on
Print_ISBN :
0-7695-1881-8
DOI :
10.1109/ISQED.2003.1194755