DocumentCode :
393386
Title :
On improving FPGA routability applying multi-level switch boxes
Author :
Liu, Jiping ; Fan, Hongbing ; Wu, Yu-Liang
Author_Institution :
Lethbridge Univ., Alta., Canada
fYear :
2003
fDate :
21-24 Jan. 2003
Firstpage :
366
Lastpage :
369
Abstract :
In this paper, we propose a new FPGA switch box design style - the extended switch boxes. An extended switch box is multi-level in nature. It consists of a kernel and extension(s) connected to the kernel, while many conventional switch boxes only consist of the kernel part and are referred to as single-level switch boxes. We show that with a much reduced total number of manufactured switches in the chip, this new design has a guaranteed complete mappability from any global routing to a feasible detailed routing of the entire FPGA chip. The interesting results seem to open a new avenue for designing FPGA routing structures.
Keywords :
circuit optimisation; field programmable gate arrays; integrated circuit design; logic design; network routing; FPGA chip detailed routing structures; FPGA routability; chip switch number reduction; complete mappability; extended switch boxes; global routing; kernel extensions; multi-level switch boxes; optimum routing; single-level switch boxes; Boolean functions; Field programmable gate arrays; Kernel; Logic; Manufacturing; Pins; Routing; Switches; Topology; Wire;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference, 2003. Proceedings of the ASP-DAC 2003. Asia and South Pacific
Print_ISBN :
0-7803-7659-5
Type :
conf
DOI :
10.1109/ASPDAC.2003.1195042
Filename :
1195042
Link To Document :
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