A low-power architecture for maximum a posteriori decoding

In this paper, we present a novel architecture for soft-input soft-output (SISO) maximum a posteriori (MAP) decoding. The architecture leverages an ASIP (application specific instruction-set processor) structure, where the datapath has been designed to achieve high-speed performance and low power dissipation. Salient features of this architecture include: (a) delayed renormalization of the /spl alpha/ metrics with register bypassing to reduce latency, (b) use of register files to minimize power dissipation, and (c) microprogrammed control to achieve flexibility. The resulting architecture for the SISO-MAP decoder achieves a maximum throughput of 10.9 Msymbols/second, operating at 142 MHz and dissipating 21 mW in the datapath.