Energy minimization of a pipelined processor using a low voltage pipelined cache

A cache is a power-hungry component in a processor. Therefore, a reduction in cache energy can have a significant impact on overall processor energy consumption. In this paper, we propose a new energy minimization technique for a pipelined processor using a low voltage pipelined cache. We consider a case where a pipelined cache is not required but is used nonetheless, enabling the cache supply voltage to be lowered. Using this method, five benchmarks show that power consumption is reduced by 24.85% at a cost of an average increase in execution time of 15.35% resulting in an average overall energy reduction of 13.33%.