Using variable length coefficients to design low-space FIR filters for FPGAs

We propose a method for designing a filter to meet a set of specifications that is area-efficient. Our approach reduces the complexity of the realized digital FIR filter to give a good design with low round-off noise, low coefficient sensitivity and small order. Unlike conventional approaches, the design is based on a variable precision method that reduces the word-length of the coefficients to reduce the complexity required to implement the FIR filter. In addition, we apply a low sensitivity structure with only a small number of taps so that the specification is satisfied while simultaneously reducing the resulting hardware area required by the implementation. Some examples are given to show the effectiveness of our design.