Product level verification of gate oxide reliability projections using DRAM chips

Gate oxide reliability of DRAM products is usually predicted from test structures. In order to understand the relevance of these predictions, a verification at product level is needed. For DRAMs the wordline driver circuit is critical because it involves the highest voltage on the chip and the NFETs of this circuit have nearly 100% duty factor. Specially bonded DRAM chips were subjected to a standby stress with an externally applied boosted wordline voltage above burn-in conditions. Standard product test and additional current measurements were used to characterize the chips at each readout. Current degradation is used to demonstrate the proper stress. Failures were physically localized to distinguish between possible gate oxide in the devices under investigation and other failures. No gate oxide failures were found during the stress time, which was longer than the best-case projection from test structures. Circuit simulations as well as post breakdown resistance considerations and post breakdown device characteristics helped to understand the impact of breakdown. Long-term stress data of packaged test structures show consistent behavior with a 1/Vg-model, which could explain the product stress results.