Title :
Input/output complexity of bit-level VLSI array architectures
Author :
Burleson, Wayne P. ; Scharf, Louis L.
Author_Institution :
University of Colorado
Keywords :
Array signal processing; Computer architecture; Computer interfaces; Delay; Digital signal processing; Electronics packaging; Hardware; Iterative algorithms; Signal processing algorithms; Very large scale integration;
Conference_Titel :
Signals, Systems and Computers, 1989. Twenty-Third Asilomar Conference on
Print_ISBN :
0-929029-30-1
DOI :
10.1109/ACSSC.1989.1200826
