Title :
High performance IDCT realization using complex arithmetic
Author :
Wong, Kar-Lik ; Topham, Nigel
Author_Institution :
Siroyan Ltd., Reading, UK
Abstract :
We describe a high performance IDCT realization using complex arithmetic. The algorithm is based on novel factorization of the IDCT designed to exploit the complex multiplication capability provided by the OneDSP processor. We show a very efficient loop schedule implementing an 8-point IDCT in 9 cycles in each cluster. A single cluster OneDSP processor running at 300 MHz is capable of decoding MPEG2 bit-streams at ATSC resolutions. Error analysis of the algorithm based on IEEE 1180 compliance testing is presented.
Keywords :
data compression; decoding; digital arithmetic; digital signal processing chips; discrete cosine transforms; error analysis; inverse problems; transform coding; video coding; 300 MHz; ATSC resolutions; IDCT factorization; IEEE 1180 compliance testing; MPEG2 bit-streams decoding; OneDSP processor; complex arithmetic; efficient loop schedule; error analysis; inverse discrete cosine transform; video coding standards; Algorithm design and analysis; Arithmetic; Clustering algorithms; Computer architecture; Decoding; Error analysis; Matrix decomposition; Parallel processing; Processor scheduling; Testing;
Conference_Titel :
Acoustics, Speech, and Signal Processing, 2003. Proceedings. (ICASSP '03). 2003 IEEE International Conference on
Print_ISBN :
0-7803-7663-3
DOI :
10.1109/ICASSP.2003.1202357
