Concurrent interleaving architectures for high-throughput channel coding

Interleavers are widely used for a vast range of communications applications. Traditionally used for burst-error separation in distorted channels, they have gained additional interest since the discovery of turbo codes whose performance essentially depends on the interleavers. With the ever increasing data rates demanded by customers, architectures that provide interleaving at high throughput become mandatory. We present an heuristic approach to the design of interleaving architectures based on random graph generation. They can handle any given interleaver pattern and allow for any parallelization degree, and hence speed-up, of the interleaving operation. Moreover, this enables highly parallel architectures for channel decoders such as turbo- and LDPC-decoders.