Advanced self-organizing maps using binary weight vector and its digital hardware design

Many co-processors which are designed for learning of self-organizing maps (SOM) have been proposed in order to reduce the processing time. However, hardware in which all processes of the learning of the SOM are achieved is not realized, because it needs many complex calculations. In this study, a new learning algorithm of the SOM in which input vectors and weight vectors are represented as binary data is proposed. The effectiveness of the proposed algorithm is verified by designing the digital hardware of the proposed algorithm using HDL.