A highly linear front-end based on a logarithmic multiplier-filter

Author

Kathiresan, G. ; Drakakis, E.M. ; Toumazou, C.

Author_Institution

Toumaz Technol. Ltd., Culham, UK

Volume

1

fYear

2003

fDate

25-28 May 2003

Abstract

This paper describes a front-end suitable for operation in the 133 MHz ISM band that contains a low noise amplifier (LNA) followed by a current-mode multiplier-filter block that uses bipolar transistors operating in log-domain. Since the multiplier and filter blocks are implementing a log-domain topology, they possess high linearity. The 1 dB compression point of the overall front-end is -21 dBm, which is mainly limited by the LNA. The front-end provides a gain of 35 dB, while the IF filter has a low pass characteristic with a bandwidth of 30 MHz, making it suitable for use in a low-IF receiver.

Keywords

analogue multipliers; bipolar transistors; current-mode circuits; intermediate-frequency amplifiers; low-pass filters; network topology; radiofrequency amplifiers; 133 MHz; 30 MHz; 35 dB; IF filter low pass characteristic; ISM band operation; LNA; compression point; current-mode multiplier-filter block; filter bandwidth; filter blocks; front-end gain; highly linear front-end; log-domain operating bipolar transistors; log-domain topology; logarithmic multiplier-filter; low noise amplifier; low-IF receiver; multiplier blocks; wireless receivers; Bandwidth; Bipolar transistors; Circuits; Filtering; Linearity; Low pass filters; MOSFETs; Power harmonic filters; Radio frequency; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on

Print_ISBN

0-7803-7761-3

Type

conf

DOI

10.1109/ISCAS.2003.1205487

Filename

1205487