A high-resolution and fast-conversion time-to-digital converter

Author

Hwang, Chorng-Sii ; Chen, Poki ; Tsao, Hen-Wai

Author_Institution

Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan

Volume

1

fYear

2003

fDate

25-28 May 2003

Abstract

This paper describes a design of time-to-digital converter (TDC), which has the features of high-resolution and fast conversion. With the aid of the gate delay difference technique, the TDC can achieve a sub-gate delay resolution. The flash-type operation enables the TDC to resolve the time difference for fine conversion in less than one reference clock cycle. The differential non-linearity (DNL) can be less than ±0.03 LSB and integral non-linearity (INL) less than ±0.04 LSB. We confirm the results based on 0.35 μm CMOS process technology.

Keywords

CMOS integrated circuits; analogue-digital conversion; circuit simulation; clocks; delays; integrated circuit design; integrated circuit modelling; signal resolution; 0.35 micron; CMOS process technology; DNL; INL; differential nonlinearity; fine conversion time difference; flash-type operation; gate delay difference technique; high-resolution fast-conversion time-to-digital converter; integral nonlinearity; reference clock cycle; sub-gate delay resolution; time-to-digital converter design; CMOS process; Clocks; Counting circuits; Delay lines; Dynamic range; Phase measurement; Signal resolution; Time measurement; Timing; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on

Print_ISBN

0-7803-7761-3

Type

conf

DOI

10.1109/ISCAS.2003.1205494

Filename

1205494