A digitally skew correctable multi-phase clock generator using a master-slave DLL

This paper presents a digitally skew correctable multi-phase clock generator using a master-slave delay-locked-loop(DLL). The multi-phase clock generator is for a distributed S/H stage in interleaved ADC´s. The delay of the slave DLLs, whose outputs are used for S/H circuits, is controlled by a very short pulse generated by a master DLL. This technique allows us to control the skew of the multi-phase clocks with the resolution of less than 1 ps. The master-slave DLL also has a good stability to the power supply fluctuations. Simulation results show that the clock skew can be corrected with the resolution of 0.2ps using a current output DAC with a resolution of 0.1 μA.