A digitally skew correctable multi-phase clock generator using a master-slave DLL

Author

Suzuki, Atsushi ; Kawahito, Shoji ; Miyazaki, Daisuke ; Furuta, Masanori

Author_Institution

Shizuoka Univ., Japan

Volume

1

fYear

2003

fDate

25-28 May 2003

Abstract

This paper presents a digitally skew correctable multi-phase clock generator using a master-slave delay-locked-loop(DLL). The multi-phase clock generator is for a distributed S/H stage in interleaved ADC´s. The delay of the slave DLLs, whose outputs are used for S/H circuits, is controlled by a very short pulse generated by a master DLL. This technique allows us to control the skew of the multi-phase clocks with the resolution of less than 1 ps. The master-slave DLL also has a good stability to the power supply fluctuations. Simulation results show that the clock skew can be corrected with the resolution of 0.2ps using a current output DAC with a resolution of 0.1 μA.

Keywords

analogue-digital conversion; clocks; delay lock loops; digital-analogue conversion; sample and hold circuits; DAC; digitally skew correctable multi-phase clock generator; distributed S/H circuit; interleaved ADC; master-slave delay-locked-loop; Circuit simulation; Circuit stability; Clocks; Delay; Fluctuations; Master-slave; Power supplies; Pulse circuits; Pulse generation; Pulsed power supplies;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on

Print_ISBN

0-7803-7761-3

Type

conf

DOI

10.1109/ISCAS.2003.1205511

Filename

1205511