Title :
Timing-mismatch analysis in high-speed analog front-end with nonuniformly holding output
Author :
Sin, Sai-Weng ; Seng-Pan, U. ; Martins, R.P. ; Franca, J.E.
Author_Institution :
Fac. of Sci. & Technol., Univ. of Macau, China
Abstract :
This paper presents a practical and complete analysis of timing-mismatch effects for high-speed analog front-end (AFE) systems with inherent nonuniformly holding outputs. The analysis reveals first the relationship with traditional impulse-sampled timing-mismatch effects and then its closed-form expressions of the signal-to-noise-ratio (SNR), in terms of the number of channels, signal frequency, and jitter errors. Both timing errors imposed by random clock-jitter and fixed periodic clock-skew are analyzed. Practical analysis examples for a very high-speed data-converter as well as a AFE filtering are addressed to illustrate the effectiveness of the derived formula.
Keywords :
analogue-digital conversion; band-pass filters; circuit simulation; clocks; digital-analogue conversion; network analysis; sample and hold circuits; timing; timing jitter; ADC; AFE filtering; DAC; SNR; channel number; fixed periodic clock-skew; high-speed analog front-end; impulse-sampled timing-mismatch effects; jitter errors; multirate bandpass interpolating filter; nonuniformly holding output front-end; random clock-jitter; sample-and-hold circuits; signal frequency; signal-to-noise-ratio; timing errors; timing-mismatch analysis; very high-speed data-converter; Analog-digital conversion; Clocks; Closed-form solution; Frequency; Image sampling; Jitter; Signal analysis; Signal processing; Signal sampling; Signal to noise ratio;
Conference_Titel :
Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on
Print_ISBN :
0-7803-7761-3
DOI :
10.1109/ISCAS.2003.1205517