Design of a digitally programmable delay-locked-loop for a low-cost ultra wide band radar receiver

This paper presents a digitally programmable delay line intended for use as a timing generator in a RADAR ranging system. Traditional delay lines are realized selecting the delayed signal from a tap in a cascade of delay elements, resulting in a delay resolution limited by the matching errors between the delay elements. The architecture of the programmable delay line presented in this paper uses a ΣΔ modulator to generate a delay unaffected by matching and a delay locked loop to filter the excess jitter noise from the output clock. System level simulations show that it is possible to obtain a resolution of 11 bits corresponding to an average output rms jitter noise of 11.4 ps.