Design of enhancement current-balanced logic for mixed-signal ICs

Author

Yang, Li ; Yuan, J.S.

Author_Institution

Sch. of Electr. Eng. & Comput. Sci., Univ. of Central Florida, Orlando, FL, USA

Volume

1

fYear

2003

fDate

25-28 May 2003

Abstract

The dual-V_T and negative feedback mechanisms have been proposed to enhance Current Balanced Logic (CBL) for low noise IC design. The detailed circuit analysis and SPICE simulations show that the dual-V_T structure has advantages over the conventional CBL design in many design aspects, such as gate area, delay, power dissipation, and switching noise. The negative feedback can further reduce the current spike with some tradeoffs. The design procedures of the enhancement CBL are discussed in detail. The proposed methods give the designer a better control of the current spike for mixed-signal integrated circuits.

Keywords

MOS logic circuits; circuit feedback; circuit optimisation; integrated circuit noise; logic design; mixed analogue-digital integrated circuits; current spike control; delay; dual threshold voltage structure; dual-V_T structure; enhancement current-balanced logic; gate area; low noise IC design; mixed-signal ICs; mixed-signal integrated circuits; negative feedback mechanisms; power dissipation; switching noise; Analytical models; Circuit analysis; Circuit simulation; Delay; Integrated circuit noise; Logic design; Negative feedback; Power dissipation; SPICE; Switching circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on

Print_ISBN

0-7803-7761-3

Type

conf

DOI

10.1109/ISCAS.2003.1205675

Filename

1205675