Title :
Design techniques for a fully differential low voltage low-power flash analog to-digital converter
Author :
Lee, Tsung-Sum ; Luo, Li-Dyi ; Lin, Chin-Sheng
Author_Institution :
Dept. of Electron. Eng., Nat. Yunlin Univ. of Sci. & Technol., Taiwan
Abstract :
A CMOS 8-bit, 33.3MS/s flash ADC with ±1.5V power supply is developed through the use of a low-power high-speed CMOS fully differential comparator. To achieve good signal-to-(noise and distortion) ratio in the presence of noisy digital circuitry, the architecture of the ADC is fully differential. The differential nonlinearity error in dynamical operation is less than ±0.3LSB. Signal-to-(noise and distortion) ratio is 46.2dB at a sampling rate of 33.3MS/s and input frequency of 4MHz. The power dissipation is 106mW at 33.3MS/s with ±1.5V power supply.
Keywords :
CMOS integrated circuits; analogue-digital conversion; comparators (circuits); high-speed integrated circuits; low-power electronics; 1.5 V; 106 mW; 4 MHz; 8 bit; CMOS flash analog-to-digital converter; design technique; differential nonlinearity error; low-voltage low-power high-speed fully-differential comparator; power dissipation; signal-to-noise-and-distortion ratio; Analog-digital conversion; Circuits; Decoding; Distortion; Inverters; Power dissipation; Power supplies; Sampling methods; Signal to noise ratio; Voltage;
Conference_Titel :
Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on
Print_ISBN :
0-7803-7761-3
DOI :
10.1109/ISCAS.2003.1205690
