DocumentCode
396428
Title
A digital background calibration technique for pipelined analog-to-digital converters
Author
Liu, Hung-Chih ; Lee, Zwei-Mei ; Wu, Jieh-Tsorng
Author_Institution
Dept. of Electron. Eng., Nat. Chiao-Tung Univ., Hsin-Chu, Taiwan
Volume
1
fYear
2003
fDate
25-28 May 2003
Abstract
A new background calibration technique for pipelined analog-to-digital converters is proposed. By dividing the step sizes of the multiplying digital-to-analog converter (MDAC) in a pipeline stages and injecting a random signal into the MDAC, it is possible to calibrate a pipeline stage without interrupting the normal analog-to-digital operation. The calibration can eliminate the nonlinear effects due to the MDAC´s gain error, input offset voltage, and output errors in the digital-to-analog conversion.
Keywords
analogue-digital conversion; calibration; pipeline processing; digital background calibration; multiplying digital-to-analog converter; pipelined analog-to-digital converter; Analog-digital conversion; CMOS technology; Calibration; Capacitors; Clocks; Degradation; Pipelines; Power dissipation; Sampling methods; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on
Print_ISBN
0-7803-7761-3
Type
conf
DOI
10.1109/ISCAS.2003.1205705
Filename
1205705
Link To Document