Dual-mode sigma-delta modulator for wideband receiver applications

Author

Chiang, Jen-Shiun ; Chou, PaeChu ; Chang, Teng-Hung

Author_Institution

Dept. of Electr. Eng., Tamkang Univ., Tamsui, Taiwan

Volume

1

fYear

2003

fDate

25-28 May 2003

Abstract

This work presents a new sigma-delta modulator (SDM) architecture for wide bandwidth receiver, which contains dual-bandwidth for WCDMA and GSM system applications. This is a multistage architecture with a low-distortion swing-suppressing SDM and an interpolative SDM cascaded together. By the low-distortion and swing-suppressing technique, the resolution can be improved even under non-linearity effects. The interpolative SDM is to repress the high-band noise. The proposed SDM was designed and simulated by the 0.25-μm 1P5M CMOS technology. The simulated peak SNDR for WCDMA is 72dB and for GSM is 82dB.

Keywords

CMOS integrated circuits; cellular radio; code division multiple access; integrated circuit noise; radio receivers; sigma-delta modulation; 0.25 micron; 1P5M CMOS technology; GSM; WCDMA; dual-mode sigma-delta modulator; high-band noise; interpolative SDM; low-distortion swing-suppressing SDM; multistage architecture; nonlinearity effects; wide bandwidth receiver; wideband receiver applications; Bandwidth; CMOS technology; Circuits; Delta-sigma modulation; GSM; Multi-stage noise shaping; Multiaccess communication; Radio frequency; Wideband; Wireless communication;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on

Print_ISBN

0-7803-7761-3

Type

conf

DOI

10.1109/ISCAS.2003.1205734

Filename

1205734