Implementing Otsu´s thresholding process using area-time efficient logarithmic approximation unit

Otsu´s global automatic image thresholding method has been widely employed in various real-time applications. In this paper, a novel architecture for the BCVC (Between Class Variance Computation) of Otsu´s method is presented to meet these high-speed requirements. The proposed implementation employs a binary Logarithmic Conversion Unit (LCU) to eliminate the complex divisions and multiplications in the Otsu´s procedure. Implementations on the FPGA (Field Programmable Gate Array) platform show that our method achieves a computation speed-up of about 2.75 times by occupying only 1/6^th of the FPGA slices required by one that relies on the direct implementation.