eUTDSP: a design study of a new VLIW-based DSP architecture

Author

Chaji, G.R. ; Pourrad, R.M. ; Fakhraie, S.M. ; Tehranipour, M.H.

Author_Institution

VLSI Circuits & Syst. Lab., Tehran Univ., Iran

Volume

4

fYear

2003

fDate

25-28 May 2003

Abstract

This paper presents a new DSP architecture called eUTDSP that is based on a traditional VLlW architecture. It is able to perform maximum of 4 instructions per cycle with a 128-bit instruction word size. VLlW systems usually suffer from the disadvantage of larger program memories due to longer instructions. As well, branches usually have some added delay slots and this also causes more drawbacks. In order to solve such problems, some architectural solutions are presented in this paper Benchmarking results obtained from VHDL and C++ models show the efficiency of eUTDSP for better utilization of functional units in each cycle, code size shrinking and reducing branch/loop overheads.

Keywords

digital signal processing chips; instruction sets; parallel architectures; 128 bit; C++ models; VLIW-based DSP architecture; architectural solutions; branch/loop overheads; code size shrinking; delay slots; eUTDSP; functional units; instruction word size; Application software; Circuits and systems; Digital signal processing; Digital signal processing chips; Hardware; Laboratories; Program processors; Programming profession; VLIW; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on

Print_ISBN

0-7803-7761-3

Type

conf

DOI

10.1109/ISCAS.2003.1205792

Filename

1205792