eUTDSP: a design study of a new VLIW-based DSP architecture

This paper presents a new DSP architecture called eUTDSP that is based on a traditional VLlW architecture. It is able to perform maximum of 4 instructions per cycle with a 128-bit instruction word size. VLlW systems usually suffer from the disadvantage of larger program memories due to longer instructions. As well, branches usually have some added delay slots and this also causes more drawbacks. In order to solve such problems, some architectural solutions are presented in this paper Benchmarking results obtained from VHDL and C++ models show the efficiency of eUTDSP for better utilization of functional units in each cycle, code size shrinking and reducing branch/loop overheads.