DocumentCode
396587
Title
Design of CMOS CML circuits for high-speed broadband communications
Author
Green, Michael M. ; Singh, Ullas
Author_Institution
Dept. of Electr. & Comput. Eng., California Univ., Irvine, CA, USA
Volume
2
fYear
2003
fDate
25-28 May 2003
Abstract
This paper discusses the behavior and design of CMOS current-mode logic (CML) circuits. The advantages of using the CML topology over static CMOS for high-speed digital signals are discussed. Biasing and dynamic behavior of CML circuits are discussed and a design method for optimizing the bandwidth and speed is presented.
Keywords
CMOS logic circuits; SONET; circuit optimisation; current-mode logic; high-speed integrated circuits; integrated circuit design; jitter; logic design; transceivers; CML topology; CMOS current-mode logic circuits; SONET; all-CMOS transceivers; bandwidth optimization; biasing; design method; deterministic jitter; dynamic behavior; high-speed broadband communications; high-speed digital signals; speed optimization; Broadband communication; CMOS logic circuits; Circuit noise; Circuit topology; Jitter; Logic circuits; Logic design; Logic gates; Signal processing; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on
Print_ISBN
0-7803-7761-3
Type
conf
DOI
10.1109/ISCAS.2003.1205937
Filename
1205937
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