Title :
Parallel bus systems using code-division multiple access technique
Author :
Shimizu, Shinsaku ; Matsuoka, Toshimasa ; Taniguchi, Kenji
Author_Institution :
Dept. of Electron. & Inf. Syst., Osaka Univ., Japan
Abstract :
For VLSI systems the parallel bus interface using the CDMA technique is proposed, which has low power consumption and high noise tolerance. The proposed interface can transfer data between a transmitter and a receiver in one clock. It has tolerance to the timing variation in the signal transfer among every buses which is an advantage compared with conventional parallel bus. The 15 bit parallel CDMA bus interface with the access speed of 2.5 Gb/s had been successfully implemented with 0.35 μm CMOS technology.
Keywords :
CMOS digital integrated circuits; VLSI; code division multiple access; high-speed integrated circuits; low-power electronics; pseudonoise codes; receivers; system buses; transmitters; 0.35 micron; 2.5 Gbit/s; CDMA technique; VLSI systems; data transfer; high noise tolerance; low power consumption; parallel bus interface; receiver; timing variation; transmitter; CMOS technology; Clocks; Energy consumption; Information systems; Interference; Multiaccess communication; Timing; Transmitters; Very large scale integration; Wireless communication;
Conference_Titel :
Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on
Print_ISBN :
0-7803-7761-3
DOI :
10.1109/ISCAS.2003.1205949
