A novel ACS scheme for area-efficient Viterbi decoders

Author

Zhu, Y. ; Benaissa, M.

Author_Institution

Dept. of Electron. & Electr. Eng., Univ. of Sheffield, UK

Volume

2

fYear

2003

fDate

25-28 May 2003

Abstract

This paper presents a novel ACS (add-compare-select) scheme that enables high-speeds to be achieved in area-efficient Viterbi decoders without compromising area and power efficiency. This is achieved by introducing multi-level pipelining into the ACS feedback loop. As a proof of concept, a constraint-7 Viterbi decoder using 8 ACS units has been designed with 5 pipeline levels. This design has been implemented successfully on an FPGA device. The results obtained confirm functionality, speed improvements and the expected low resource usage. To quantify these, a state-parallel Viterbi decoder design has also been implemented on the same FPGA device and performance comparisons made.

Keywords

Viterbi decoding; circuit feedback; field programmable gate arrays; logic design; pipeline arithmetic; ACS feedback loop; ACS scheme; FPGA implementation; add-compare-select scheme; area-efficient Viterbi decoders; constraint-7 Viterbi decoder; multilevel pipelining; power efficiency; resource usage; state-parallel Viterbi decoder; Computer architecture; Convolutional codes; Costs; Decoding; Delay; Feedback loop; Field programmable gate arrays; Pipeline processing; Scheduling; Viterbi algorithm;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on

Print_ISBN

0-7803-7761-3

Type

conf

DOI

10.1109/ISCAS.2003.1205956

Filename

1205956