A 1.35 GHz CMOS wideband frequency synthesizer for mobile communications

Author

Juárez-Hernández, Esdras ; Díaz-Sánchez, Alejandro ; Tleio-Cuautle, E.

Author_Institution

Univ. Autonoma de Puebla, Mexico

Volume

2

fYear

2003

fDate

25-28 May 2003

Abstract

The design and simulation of a 1.35 GHz fully integrated CMOS frequency synthesizer for a double band receiver is presented. The proposed synthesizer is based on a wide-band PLL topology with a high. reference frequency. This approach allows obtaining low phase noise, fast switching time, a low divider ratio and a reduction in the total chip area. Besides, the use of a novel charge-pump, circuit with partial positive feedback and current reuse allows a further reduction in both chip area and power consumption, making the proposed structure suitable for high frequency and low-voltage phase-locked loops.

Keywords

CMOS analogue integrated circuits; UHF integrated circuits; circuit feedback; frequency synthesizers; mobile communication; phase locked loops; phase noise; 1.35 GHz; CMOS wideband frequency synthesizer; charge-pump circuit; chip area; current reuse; divider ratio; double band receiver; mobile communications; partial positive feedback; phase noise; power consumption; reference frequency; switching time; total chip area; wide-band PLL topology; Charge pumps; Circuit topology; Communication switching; Feedback circuits; Feedback loop; Frequency synthesizers; Mobile communication; Phase locked loops; Phase noise; Wideband;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on

Print_ISBN

0-7803-7761-3

Type

conf

DOI

10.1109/ISCAS.2003.1205964

Filename

1205964