An FPGA implementation of discrete Hartley transforms

Discrete Hartley transforms (DHTs) are very important in many types of applications including image and signal processing. Two novel architectures for computing DHTs using both systolic architecture and distributed arithmetic design methodologies are presented in this paper. The first approach uses the modified Booth-encoder-Wallace trees multiplication (MBWM) algorithm for a systolic architecture implementation. The second approach is based on distributed arithmetic ROM and accumulator structure. Implementations of the algorithms on a Xilinx FPGA board are described. Distributed arithmetic approach exhibits better performances when compared with the systolic architecture approach.