Synthesis of a 12-bit complex mixer for FPGA implementation

This paper presents a FPGA implementation of a multiplier-based complex mixer for communication systems that require high-throughput rates and architecture scalability. The paper focuses on the design of a complex mixer that consists of a Baugh-Wooley-adder-tree complex multiplier and a direct digital frequency synthesizer (DDFS) based on a linear segment interpolation algorithm. The regular structure of this architecture permits deep pipelining and facilitates scaling to meet a given system specification.