High speed GAML-based phylogenetic tree reconstruction using HW/SW codesign

Heuristics for reconstructing the phylogenetic tree of DNA sequences based on maximum likelihood are computationally expensive. The tree evaluation function that calculates the likelihood value for each tree topology dominates the time in searching the optimal tree. We developed a hybrid hardware/software (HW/SW) system for solving the phylogenetic tree reconstruction problem using the genetic algorithm for maximum likelihood (GAML) approach. The GAML is partitioned into a genetic algorithm (GA) and a fitness evaluation function, with the SW handling the GA and the HW evaluating the maximum likelihood function. This approach exploits the flexibility of software and the speed up of high performance hardware. An efficient field programmable gate arrays (FPGA) implementation for the required computation on evolution tree topology fitness evaluation is proposed. The complete high-level digital design is developed and Xilinx´s Java-based JBits toolkit is used for constructing a BRAM interface for digital process synchronization control and GA chromosomes transmission between a workstation and the Xilinx Virtex-800 FPGA processor. This implementation provides approximately 30 to 100 times in speedup improvement when compared to a software solution.